It is well known that dynamic or volatile semiconductor memories employed as the main memory of an electronic data processing or computer system, for example, a microcomputer, must be periodically refreshed in order to prevent volatilization of the contents of the memory. However, in the past, this refresh function has been provided by special refresh control logic which periodically generates refresh read cycles. Such control logic typically contains the following functions and/or circuits:
arbitration of requests from the central processing unit (CPU) for memory cycles and refresh requests for memory cycles;
a refresh address register and counter; and
Circuits for multiplexing the refresh address onto the memory address bus.
The prior art is replete with such special refresh control circuits, as exemplified by the following U.S. Pat. Nos. 3,999,170; 4,142,233; 4,158,883; 4,185,323; and 4,207,618.